/**
 ** 存储空间驱动器，负责读写数据
 ** a端口用来写，b端口用来读
**/
module memoryWorker (
    input wire clk,
    input wire rst,
    input wire wr_padding_en,
    input wire wr_en,
    input wire [12:0] wr_address,
    input wire [31:0] wr_data,
    input wire rd_en,                         
    input wire [12:0] rd_address,        
    output reg ena,
    output reg wea,
    output reg [12:0] addra,
    output reg [31:0] dina,
    output reg enb,
    output reg web,
    output reg [12:0] addrb,
    output reg [31:0] dinb
);
    //读逻辑
    always @(posedge clk) begin
        if (rd_en) begin
            enb <= 1'b1;
            web <= 1'b0;
            dinb <= 0;
            addrb <= rd_address;
        end
        else begin
            dinb <= 0;
            enb <= 1'b0;
        end
    end

    //写逻辑
    always @(posedge clk) begin
        if (wr_en) begin
            ena <= 1'b1;
            wea <= 1'b1;
            addra <= wr_address;
            if (wr_padding_en) begin
                dina <= 32'hffff;
            end
            else begin
                dina <= wr_data;
            end
        end
        else begin
            ena <= 1'b0;
            wea <= 1'b0;
        end
    end
    
endmodule